Semiconductor chips which contain CMOS logic circuits are well known and widely used throughout the electronic industry because of their inherent high speed performance with relatively low power consumption. A single CMOS logic chip may have over one million individual CMOS devices of both PFET AND NFET type interconnected to form logic circuits e.g. logic gates which are then further interconnected to form various logic functions. The individual CMOS devices are intentionally made as small as possible in order to minimize the total semiconductor chip size and therefore the cost of a chip.
While the CMOS logic circuits are freely interconnected on a chip, when a logic signal must be sent to another chip, then additional driving power is required. Special driver circuits using much larger PFET AND NFET drivers are constructed on the chip in order to handle the increased driving power needed. A driver circuit may need to drive a transmission line with or without terminations. The transmission line may be part of a bus with multiple drivers connected or tapped on at various points, each one increasing the load capacitance which must be driven.
In addition, each driver must normally be capable of entering a tristate mode when not active in order to prevent a conflict with another driver on the bus which is currently active. The driver may also need to provide a termination for the transmission line a described in U.S. Pat. No. 4,859,877 which is incorporated by reference herein.
The driver circuits are of such a high power that they can not be driven directly by ordinary logic gates on the CMOS chip and accordingly a predriver circuit is used between the output of an ordinary logic gate on the chip and the inputs of a driver circuit. As shown in U.S. Pat. No. 5,381,059 there are usually two inputs to a driver circuit, one for the large NFET pull-down device and one for the large PFET pull-up device.
The predriver circuit therefore has two outputs and two or more inputs. The inputs are the data signal, a tristate mode signal and optionally various enable signals or signals to provide a termination function for cases where the driver is located at the end of a transmission line.
Driving the gate of a large PFET pull-up device of the driver circuit to an up level is a problem for a predriver circuit. In order to rapidly pull the gate of the driver PFET device to the upper supply rail, a relatively large PFET device is needed in the predriver circuit. Larger devices tend to be slower so that increasing the predriver PFET size to increase pull-up current does not necessarily result in faster operation.
In cases where supply current transients are more important than operating speed, such as occurs with packages having a relatively large supply inductance, pull up action is intentionally delayed to reduce the effect of noise on other circuits. Boler et al. in U.S. Pat. No. 4,638,187, Yu et al. in U.S. Pat. No. 4,800,298, and Sood in U.S. Pat. No. 4,724,340 all use a PFET driven by an inverted delayed signal, in parallel with an NFET as a pull-up which reduces supply transients. Walters, Jr. in U.S. Pat. No. 5,041,738 uses programmable fuses to control the delay of the rise of a pull-up circuit.
The overall operating speed of a system with the predrive-driver combination is limited by both the slew rate and delay of the driver circuit as well as the time required to enter and return from tristate mode. Usually this mode switching becomes the limiting factor. Therefore it would be advantageous to match the mode switching speed to the operational switching speed so that neither one imposes a significant limitation.
In accordance with the teachings of the present invention, there is defined a new CMOS predriver circuit which includes capability for rapid pull-up of the gate of a driver PFET device and capability for matching mode switching speed to operational speed. It is believed that such a circuit constitutes a significant advancement in the art.